1. Field of the Invention
The present invention relates to an electronic display device fabricated by forming EL (electroluminescence) elements on a substrate, specifically, to an EL display device using a semiconductor element (an element formed from a semiconductor thin film). The invention also relates to electronic equipment employing the EL display device as a display unit.
The EL element herein includes both an element that utilizes light emission from a singlet exciton (fluorescence) and an element that utilizes light emission from a triplet exciton (phosphorescence).
2. Description of the Related Art
Development of EL display devices having an EL element as a self-luminous element is flourishing in recent years. The EL display devices are also called organic EL displays (OELDS) or organic light emitting diodes (OLEDs).
The EL display devices are self-luminous unlike liquid crystal display devices. The EL element is structured such that an EL layer is sandwiched between a pair of electrodes (an anode and a cathode). The EL layer usually has a laminate structure. Typical example thereof is a laminate structure consisting of a hole transportation layer, a light emitting layer and an electron transportation layer which has been proposed by Tang, et al. of Eastman Kodak Company. This structure is very high in light emission efficiency, and is employed by almost all of EL display devices currently under development.
Other examples of the structure of the EL layer include a laminate structure consisting of an anode, a hole injection layer, a hole transportation layer, a light emitting layer and an electron transportation layer which are layered in this order, and a laminate structure consisting of an anode, a hole injection layer, a hole transportation layer, a light emitting layer, an electron transportation layer and an electron injection layer which are layered in this order. The light emitting layer may be doped with a fluorescent pigment or the like.
In this specification, all layers that are formed between an anode and a cathode are collectively called an EL layer. Therefore the EL layer includes all of the above hole injection layer, hole transportation layer, light, emitting layer, electron transportation layer and electron injection layer.
A pair of electrodes (a cathode and an anode) applies a given voltage to the EL layer structured as above, whereby carrier recombination takes place in the light emitting layer to cause the layer to emit light. The voltage applied between two electrodes (an anode and a cathode) of an EL element is herein referred to as EL driving voltage. An EL element emitting light is herein expressed as an EL element being driven. A light emitting element composed of an anode, an EL layer and a cathode herein will be referred to as EL element.
FIG. 4 is a block diagram showing a multi-gray scale EL display device. The display device shown here is of the type that obtains gray scale by inputting a digital signal into a source signal line driving circuit and uses a digital gray scale method. Particularly the case of using time division gray scale method for varying the luminance by controlling the period of time during which a pixel emits light will be described.
The EL display device of FIG. 4 has a pixel portion 101 and a source signal line driving circuit 102 and a gate signal line driving circuit 103 which are arranged in the periphery of the pixel portion 101. The pixel portion and the driving circuits are composed of thin film transistors (hereinafter referred to as TFTs) formed on a substrate. An external switch 116 for controlling the EL driving voltage is connected to the pixel portion 101.
The source signal line driving circuit 102 includes, basically a shift register 102a, a latch (A) 102b and a latch (B) 102c. The shift register 102a receives input of a clock signal (CLK) and a start pulse (SP). The latch (A) 102b receives input of digital data signals (denoted by VD in FIG. 4) whereas the latch (B) 102c receives input of latch signals (denoted by S_LAT in FIG. 4).
The digital data signals VD to be inputted to the pixel portion 101 are generated in a time division gray scale data signal generating circuit 114. This circuit converts video signals that are analog signals or digital signals containing image information into the digital data signals VD for time division gray scale. The circuit 114 also generates a timing pulse or the like that is necessary for time division gray scale display.
Typically, the time division gray scale data signal generating circuit 114 includes means for dividing one frame period into a plurality of sub-frame periods in accordance with n bit gray scale (n is an integer of 2 or greater), means for selecting either a writing period or a display period in each of the plural sub-frame periods, and means for setting the length of the display period.
The pixel portion 101 is structured generally as shown in FIG. 5. In FIG. 5, the pixel portion 101 is provided with gate signal lines (G1 to Gy) to which a selecting signal is inputted and source signal lines (also called data signal lines) (S1 to Sx) to which a digital data signal is inputted. The digital data signal refers to a digital video signal.
The pixel portion also has power supply lines (V1 to Vx) parallel to the source signal lines (S1 to Sx). The electric potential of the power supply lines (V1 to Vx) is called a power supply electric potential. Wirings (Vb1 to Vby) are provided in parallel with the gate signal lines (G1 to Gy). The wirings (Vb1 to Vby) are connected to the external switch 116.
A plurality of pixels 104 are arranged in matrix in the pixel portion 101. One of the pixels 104 is enlarged and shown in FIG. 6. In FIG. 6, reference symbol 1701 denotes a TFT functioning as a switching element (hereinafter referred to as switching TFT). 1702 denotes a TFT functioning as an element for controlling a current supplied to an EL element 1703 (current controlling element) (The TFT will be called a driving TFT). Designated by 1704 is a capacitor storage.
The switching TFT 1701 has a gate electrode connected to a gate signal line 1705 that is one of the gate signal lines (G1 to Gy) to which a gate signal is inputted. The switching TFT 1701 has a source region and a drain region one of which is connected to a source signal line 1706 and the other of which is connected to a gate electrode of the driving TFT 1702 and to the capacitor storage 1704. The source signal line 1706 is one of the source signal lines. (S1 to Sx) to which a digital data signal is inputted.
The driving TFT 1702 has a source region and a drain region one of which is connected to a power supply line 1707 and the other of which is connected to the EL element 1703. The power supply line 1707 is one of the power supply lines (V1 to Vx). The capacitor storage 1704 is connected to the power supply line 1707 that is one of the power supply lines (V1 to Vx).
The EL element 1703 is composed of an anode, a cathode, and an EL layer interposed between the anode and the cathode. When the anode is connected to the source region or the drain region of the driving TFT 1702, the anode serves as a pixel electrode whereas the cathode serves as an opposite electrode. On the other hand, when the cathode is connected to the source region or the drain region of the driving TFT 1702, the cathode serves as the pixel electrode whereas the anode serves as the opposite electrode. The electric potential of the opposite electrode is herein called an opposite electric potential. The difference in electric potential between the opposite electrode and the pixel electrode generates the EL driving voltage, which is applied to the EL layer.
The opposite electrode of the EL element 1703 is connected to the external switch 116 through one of the wirings (Vb1 to Vby). (See FIG. 5.) Next, driving the multi-gray scale EL display device in accordance with the time division gray scale method will be described. The description given here takes as an example the case where n bit digital video signals are inputted to obtain display in 2n gray scales.
FIG. 7 shows a timing chart thereof.
First, one frame period is divided into n sub-frame periods (SF1 to SFn).
A period during which one image is displayed using all of the pixels in the pixel portion is defined as one frame period (F). Here, one frame period is set to about 1/60 second. With the period set to this long, human eyes do not recognize flicker in animated images displayed.
As the number of gray scales is increased, the number of sub-frame periods in one frame period also increases and the driving circuits (the source signal line driving circuit and the gate signal line driving circuit), the source signal line driving circuit in particular, has to be driven at a higher frequency.
Each sub-frame period is divided into a wiring period (Ta) and a display period (Ts). The writing period is a period for inputting signals into all of the pixels in one sub-frame period. The display period (also called a lights-on period) is a period for choosing whether or not the EL element emits light so that an image is displayed.
The EL driving voltage shown in FIG. 7 corresponds to the EL driving voltage of the EL element when the EL element is caused to emit light. To elaborate, the EL driving voltage of the EL element in the pixel which is designated to emit light is in the level that does not cause the EL element to emit light, e.g., 0 V, during the writing period. During the display period, on the other hand, the EL driving voltage thereof is in the level that allows the EL element to emit light.
The opposite electric potential is controlled by the external switch 116 shown in FIGS. 4 and 5. During the writing period, the opposite electric potential is kept at the same level as the power supply electric potential. On the other hand, the opposite electric potential is changed in the display period so as to generate an electric potential difference between the opposite electric potential and the power supply electric potential which causes the EL element to emit light.
Detailed descriptions will be given first on the writing period and the display period of the respective sub-frame periods using the reference symbols in FIGS. 5 and 6. Then time division gray scale display will be described.
First, a gate signal is inputted to the gate signal line G1 to turn every switching TFT 1701 connected to the gate signal line G1 ON.
In this specification, a TFT being turned ON means that the gate voltage of the TFT is changed to make the source-drain thereof conductive.
Then the writing period is started and digital data signals are inputted to the source signal lines (S1 to Sx). At this point the opposite electric potential is kept at the same level as the power supply electric potential of the power supply lines (V1 to Vx). The digital data signals contain information of ‘0’ or ‘1’. The digital data signals of ‘0’ and ‘1’ are signals having Hi voltage and Lo voltage, respectively.
The digital data signals inputted to the source signal lines (S1 to Sx) are inputted to the gate electrode of each driving TFT 1702 through each switching TFT 1701 that has been turned ON. The capacitor storage 1704 also receives input of a digital data signal to hold it in.
Selecting signals are successively inputted to the gate signal lines G2 to Gy to repeat the above operation until all of the pixels receive input of the digital data signals and the inputted digital data signals are held in the respective pixels. A period it takes for the digital data signals to be inputted to all of the pixels in each sub-frame period is the writing period.
After inputting the digital data signals to all of the pixels, every switching TFT 1701 is turned OFF.
A TFT being turned OFF means that the gate voltage of the TFT is changed to make the source-drain thereof unconductive.
Thereafter, the external switch 116 connected to the opposite electrode is used to change the electric potential difference between the opposite electric potential and the power supply electric potential to a degree that causes the EL element to emit light.
When a digital data signal has information of ‘0’, the driving TFT 1702 is turned OFF and the EL element 1703 does not emit light. When a digital data signal has information of ‘1’ on the other hand, the driving TFT 1702 is turned ON. Then the pixel electrode of the EL element 1703 is kept at the power supply electric potential and the EL element 1703 emits light. In this way, information contained in a digital data signal determines whether the EL element emits light or not. Every pixel whose EL element is designated to emit light is simultaneously lit up, and the lit-up pixels together form an image. A period during which the display by the pixels lasts is the display period.
The writing periods (Ta1 to Tan) in the n sub-frame periods (SF1 to SFn) have the same length. The sub-frame periods SF1 to SFn have display periods Ts1 to Tsn, respectively.
For instance, the length of the display periods may be set so as to satisfy the relation Ts1:Ts2:Ts3: . . . :Ts(n−1):Tsn=20:2−1:2−2: . . . :2−(n−2):2−(n−1). Display of desired gray scales within the range of 2n gray scales can be obtained through combinations of the display periods.
Here, given pixels are lit up for the period Tsn.
Then, a writing period is started again so that all the pixels receive digital data signals to start the display period. Subsequently, one of the display periods Ts1 to Ts(n−1) is started. Here, given pixels are lit up for the period Ts(n−1).
The same operation is repeated for the remaining (n−2) sub-frame periods, so that the display periods Ts(n−2), Ts(n−3), and Ts1 are sequentially set and given pixels are lit up during each of the sub-frame periods.
One frame period is completed when n sub-frame periods have come and gone. The cumulative length of the display periods during which a pixel is lit up determines the gray scale of the pixel.
For example, the luminance is 100% when n=8 and the pixel in question emits light in all display periods. When the pixel emits light only in the display periods Ts1 and Ts2, the luminance is 75%. If the pixel is designated to emit light during the display periods Ts3, Ts5 and Ts8, the luminance may be 16%.